This application is a divisional application of U.S. Ser. No. 10/063,427, filed Apr. 23, 2002, the disclosures of which are incorporated by reference herein in their entirety.
This invention describes a system and method for locating and defining process sensitive sites isolated to specific geometries or shape configurations within the chip design data, also leveraging the knowledge of the process sensitive sites found. Process sensitive sites are defined as those areas where the design assumptions and expectations have exceeded the actual process capability.
Electrical shorts and opens parameters are impacted where the process tolerance is not design compatible. This systematic yield loss may be driven by RIE loading effects, lithographic offsets, over/under layout sensitivities, topography, pattern density, and other adjacency effects, at specific process sensitive sites. Given the compression of the yielding production ramp-up cycle, design revisions with work in progress turns are no longer an option.
Fabricators and designers commonly use tools or systems for placing shapes to improve layout sensitivity and optimize for random defect tolerance. For example, wiring layout tools will not only optimize routing for timing and reduced delay, but also to modulate defect tolerance. The defect tolerance may be analyzed by critical area versus defect size computation or optionally analyzed by the distance and run length between conductive wires susceptible to random particles. Fabricators also use tools and systems for design rule and shapes checking. Another standard methodology to compute random photo yield includes throwing random defects at-level, generating faults at the random defect sites, then selecting the faults with shape checking programs. Yield is a function of the number of faults and the size distribution.
Systematic process defects are modulated with the use of automated tools or systems to place dummy shapes or slots, place additional redundant vias or contacts or other redundant elements, and to perform layout modifications for lithographic proximity corrections, and for other RIE and lithographic effects. In the semiconductor industry, these design-for-manufacturing activities are paired with other product or design complexity analyses such as total length of routed wires, and single via count data, for example.
Computer aided design analysis tools are also utilized in industry and integrated with manufacturing and test simulators such that circuit designers can understand the impact of design issues on manufacturability of test processing.
However, the inventors are not aware any tools or systems looking for sensitivities related to structures or process and layout incompatibilities, and leveraging that information as feedforward to the designer, as well as leveraging that information in manufacturing process controls methodologies, as is described above.